Communications of the ACM
Low-power digital systems based on adiabatic-switching principles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power encodings for global communication in CMOS VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Multiplicative Masking and Power Analysis of AES
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Energy-aware design techniques for differential power analysis protection
Proceedings of the 40th annual Design Automation Conference
A New Methodology for the Design of Asynchronous Digital Circuits
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Masking the Energy Behavior of DES Encryption
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Power analysis attacks on MDPL and DRSL implementations
ICISC'07 Proceedings of the 10th international conference on Information security and cryptology
A side-channel analysis resistant description of the AES s-box
FSE'05 Proceedings of the 12th international conference on Fast Software Encryption
Pinpointing the side-channel leakage of masked AES hardware implementations
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Three-phase dual-rail pre-charge logic
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Dual-rail random switching logic: a countermeasure to reduce side channel leakage
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Security evaluation of DPA countermeasures using dual-rail pre-charge logic style
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Small size, low power, side channel-immune AES coprocessor: design and synthesis results
AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
Successfully attacking masked AES hardware implementations
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Masked dual-rail pre-charge logic: DPA-resistance without routing constraints
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
EM analysis of rijndael and ECC on a wireless java-based PDA
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Improved higher-order side-channel attacks with FPGA experiments
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Geometry of Synthesis II: From Games to Delay-Insensitive Circuits
Electronic Notes in Theoretical Computer Science (ENTCS)
Lightweight cryptography and DPA countermeasures: a survey
FC'10 Proceedings of the 14th international conference on Financial cryptograpy and data security
Security protection on FPGA against differential power analysis attacks
Proceedings of the Seventh Annual Workshop on Cyber Security and Information Intelligence Research
Randomized execution algorithms for smart cards to resist power analysis attacks
Journal of Systems Architecture: the EUROMICRO Journal
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In this paper, a new logic style is proposed to be used in the implementation of cryptographic algorithms. The aim of this approach is to counteract power analysis attacks. The proposed technique is based on the transition signaling. In dual-rail transition logic, one-bit value is transmitted by a transition on the proper signal of a couple of wires. According to this concept, converter units and logic gates are defined; it is proposed to use flip-flops to build DTL alternative parts. Although the usage of flip-flops leads to increase the required area, experimental results show that the power consumption of DTL circuits depends on unpredictable initial state of T-flip-flops. In other words, DTL randomizes the power consumption without using random number/mask generators while its delay time is reasonable in comparison with other logic styles. The difference of mean traces and the simulated attacks show that the power consumption of DTL gates does not correlate with the input/output values.