Examining Smart-Card Security under the Threat of Power Analysis Attacks
IEEE Transactions on Computers
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
Resistance against Differential Power Analysis for Elliptic Curve Cryptosystems
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Differential Power Analysis in the Presence of Hardware Countermeasures
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Energy-aware design techniques for differential power analysis protection
Proceedings of the 40th annual Design Automation Conference
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Masking the Energy Behavior of DES Encryption
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks
IEEE Transactions on Dependable and Secure Computing
Side-channel leakage of masked CMOS gates
CT-RSA'05 Proceedings of the 2005 international conference on Topics in Cryptology
Successfully attacking masked AES hardware implementations
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Masked dual-rail pre-charge logic: DPA-resistance without routing constraints
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
A secure and low-energy logic style using charge recovery approach
Proceedings of the 13th international symposium on Low power electronics and design
Power balanced gates insensitive to routing capacitance mismatch
Proceedings of the conference on Design, automation and test in Europe
Evaluation of the Masked Logic Style MDPL on a Prototype Chip
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Divided Backend Duplication Methodology for Balanced Dual Rail Routing
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Differential Capacitance Analysis
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Dual-rail transition logic: A logic style for counteracting power analysis attacks
Computers and Electrical Engineering
A countermeasure against power analysis attacks for FSR-based stream ciphers
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
An architectural countermeasure against power analysis attacks for FSR-Based stream ciphers
COSADE'12 Proceedings of the Third international conference on Constructive Side-Channel Analysis and Secure Design
A flip-flop for the DPA resistant three-phase dual-rail pre-charge logic family
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Masked dual-rail precharge logic encounters state-of-the-art power analysis methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper investigates the design of a dual-rail pre-charge logic family whose power consumption is insensitive to unbalanced load conditions thus allowing adopting a semi-custom design flow (automatic place & route) without any constraint on the routing of the complementary wires. The proposed logic is based on a three phase operation where, in order to obtain a constant energy consumption over the operating cycle, an additional discharge phase is performed after pre-charge and evaluation. In this work, the proposed concept has been implemented as an enhancement of the SABL logic with a limited increase in circuit complexity. Implementation details and simulation results are reported which show a power consumption independent of the sequence of processed data and load capacitances. An improvement in the energy consumption balancing up to 100 times with respect to SABL has been obtained.