A flip-flop for the DPA resistant three-phase dual-rail pre-charge logic family

Authors:
Marco Bucci;Luca Giancane;Raimondo Luzzi;Alessandro Trifiletti
Affiliations:
Infineon Technologies AG, Graz, Austria;Department of Electronic Engineering, University of Rome "La Sapienza", Rome, Italy;Infineon Technologies AG, Graz, Austria;Department of Electronic Engineering, University of Rome "La Sapienza", Rome, Italy
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2012

Citing 11
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Abstract

This paper investigates the design of a data flip-flop compatible with the three-phase dual-rail pre-charge logic (TDPL) family. TDPL is a differential power analysis (DPA) resistant dual-rail logic style whose power consumption is insensitive to unbalanced load conditions, based on a three phase operation where, in order to obtain a constant energy consumption, an additional discharge phase is performed after pre-charge and evaluation. In this work, the TDPL basic gates operation is shortly summarized and the TDPL flip-flop implementation is reported. A part of an encryption algorithm is used as case a study to prove the effectiveness of the proposed circuit. Simulation results in a 65 nmCMOS process show an improvement in the energy consumption balancing in excess of 10 times with respect to the state of the art.