Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware

Authors:
Kuan Jen Lin;Shan Chien Fan;Shih Hsien Yang;Cheng Chia Lo
Affiliations:
Fu Jen Catholic University, Taiwan;Fu Jen Catholic University, Taiwan;Fu Jen Catholic University, Taiwan;Fu Jen Catholic University, Taiwan
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2007

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Abstract

Cryptographic embedded systems are vulnerable to Differential Power Analysis (DPA) attacks. In this paper, we propose a logic design style, called as Precharge Masked Reed-Muller Logic (PMRML) to overcome the glitch and Dissipation Timing Skew (DTS) problems in design of DPA-resistant cryptographic hardware. Both problems can significantly reduce the DPA-resistance. To our knowledge, the DTS problem and its countermeasure have not been reported. The PMRML design can be fully realized using common CMOS standard cell libraries. Furthermore, it can be used to implement universal functions since any Boolean function can be represented as the Reed-Muller form. An AES encryption module was implemented with multi-stage PMRML. The results show the efficiency and effectiveness of the PMRML design methodology.