Interprocedural slicing using dependence graphs
ACM Transactions on Programming Languages and Systems (TOPLAS)
Advanced compiler design and implementation
Advanced compiler design and implementation
The design and use of simplepower: a cycle-accurate energy estimation tool
Proceedings of the 37th Annual Design Automation Conference
Using a High-Performance, Programmable Secure Coprocessor
FC '98 Proceedings of the Second International Conference on Financial Cryptography
DES and Differential Power Analysis (The "Duplication" Method)
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Resistance against Differential Power Analysis for Elliptic Curve Cryptosystems
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Improving Smart Card Security Using Self-Timed Circuits
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Design principles for tamper-resistant smartcard processors
WOST'99 Proceedings of the USENIX Workshop on Smartcard Technology on USENIX Workshop on Smartcard Technology
Energy-aware design techniques for differential power analysis protection
Proceedings of the 40th annual Design Automation Conference
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Security as a new dimension in embedded system design
Proceedings of the 41st annual Design Automation Conference
Design and Analysis of Dual-Rail Circuits for Security Applications
IEEE Transactions on Computers
Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Simulation models for side-channel information leaks
Proceedings of the 42nd annual Design Automation Conference
A Data-Driven Approach for Embedded Security
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Current mask generation: a transistor level security against DPA attacks
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Satisfiability-based framework for enabling side-channel attacks on cryptographic software
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
A split-mask countermeasure for low-energy secure embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware
Proceedings of the conference on Design, automation and test in Europe
RIJID: random code injection to mask power analysis based side channel attacks
Proceedings of the 44th annual Design Automation Conference
A smart random code injection to mask power analysis based side channel attacks
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Dependable and Secure Computing
Designing secure systems on reconfigurable hardware
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Dual-rail transition logic: A logic style for counteracting power analysis attacks
Computers and Electrical Engineering
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Security Primitives for Reconfigurable Hardware-Based Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A table masking countermeasure for low-energy secure embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Three-phase dual-rail pre-charge logic
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Randomized Instruction Injection to Counter Power Analysis Attacks
ACM Transactions on Embedded Computing Systems (TECS)
CLIP: circuit level IC protection through direct injection of process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Smart cards are vulnerable to both invasive and non-invasive attacks. Specifically, non-invasive attacks using power and timing measurements to extract the cryptographic key has drawn a lot of negative publicity for smart card usage. The power measurement techniques rely on the data-dependent energy behavior of the underlying system. Further, power analysis can be used to identify the specific portions of the program being executed to induce timing glitches that may in turn help to bypass key checking. Thus, it is important to mask the energy consumption when executing the encryption algorithms. In this work, we augment the instruction set architecture of a simple five-stage pipelined smart card processor with secure instructions to mask the energy differences due to key-related data-dependent computations in DES encryption. The secure versions operate on the normal and complementary versions of the operands simultaneously to mask the energy variations due to value dependent operations. However, this incurs the penalty of increased overall energy consumption in the data-path components. Consequently, we employ secure versions of instructions only for critical operations; that is we use secure instructions selectively, as directed by an optimizing compiler. Using a cycle-accurate energy simulator, we demonstrate the effectiveness of this enhancement. Our approach achieves the energy masking of critical operations consuming 83% less energy as compared to existing approaches employing dual rail circuits.