Optical Fault Induction Attacks
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
An Investigation into the Security of Self-Timed Circuits
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
CMOS Structures Suitable for Secured Hardware
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Emerging challenges in designing secure mobile appliances
Ambient intelligence
Masking the Energy Behavior of DES Encryption
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design and Analysis of Dual-Rail Circuits for Security Applications
IEEE Transactions on Computers
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Dynamic differential self-timed logic families for robust and low-power security ICs
Integration, the VLSI Journal
On the implementation of the advanced encryption standard on a public-key crypto-coprocessor
CARDIS'02 Proceedings of the 5th conference on Smart Card Research and Advanced Application Conference - Volume 5
Physical Design of FPGA Interconnect to Prevent Information Leakage
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
An EDA tool for implementation of low power and secure crypto-chips
Computers and Electrical Engineering
Novel PUF-Based Error Detection Methods in Finite State Machines
Information Security and Cryptology --- ICISC 2008
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Non-linear Error Detection for Finite State Machines
Information Security Applications
Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC
Electronic Notes in Theoretical Computer Science (ENTCS)
Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems
Proceedings of the 20th symposium on Great lakes symposium on VLSI
A first step towards automatic application of power analysis countermeasures
Proceedings of the 48th Design Automation Conference
Path swapping method to improve DPA resistance of quasi delay insensitive asynchronous circuits
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Java type confusion and fault attacks
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
Small size, low power, side channel-immune AES coprocessor: design and synthesis results
AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
Masked dual-rail pre-charge logic: DPA-resistance without routing constraints
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
The “backend duplication” method
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Secure AES hardware module for resource constrained devices
ESAS'04 Proceedings of the First European conference on Security in Ad-hoc and Sensor Networks
Evaluation metrics of physical non-invasive security
WISTP'10 Proceedings of the 4th IFIP WG 11.2 international conference on Information Security Theory and Practices: security and Privacy of Pervasive Systems and Smart Devices
An emerging threat: eve meets a robot
INTRUST'10 Proceedings of the Second international conference on Trusted Systems
EM probes characterisation for security analysis
Cryptography and Security
Cryptography with asynchronous logic automata
Cryptography and Security
Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling
ACM Transactions on Embedded Computing Systems (TECS)
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We demonstrate how 1-of-n encoded speed-independent circuits provide a good framework for constructing smart card functions that are resistant to side channel attacks and fault injection. A novel alarm propagation technique is also introduced. These techniques have been used to produce a prototype smart card chip: a 16-bit secure processor with Montgomery modular exponentiator and smart card UART.