Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems

Authors:
Jun Wu;Yong-Bin Kim;Minsu Choi
Affiliations:
Missouri University of Science & Technology, Rolla, MO, USA;Northeastern University, Boston, MA, USA;Missouri University of Science & Technology, Rolla, MO, USA
Venue:
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Year:
2010

Citing 9
Cited 1

NULL Convention Logic/sup TM/: A Complete And Consistent Logic For Asynchronous Digital Circuit Synthesis

ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Improving Smart Card Security Using Self-Timed Circuits

ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation

Proceedings of the conference on Design, automation and test in Europe - Volume 1
Automated energy calculation and estimation for delay-insensitive digital circuits

Microelectronics Journal
Designing Asynchronous Circuits using NULL Convention Logic (NCL)

Designing Asynchronous Circuits using NULL Convention Logic (NCL)
Side-channel leakage of masked CMOS gates

CT-RSA'05 Proceedings of the 2005 international conference on Topics in Cryptology
Successfully attacking masked AES hardware implementations

CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Masked dual-rail pre-charge logic: DPA-resistance without routing constraints

CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Prototype IC with WDDL and differential routing – DPA resistance assessment

CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems

Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic

Microelectronics Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this work, a novel asynchronous combinational S-Box (substitution box) design for AES (Advanced Encryption Standard) cryptosystems is proposed and validated. The S-Box is considered as the most critical component in AES crypto-circuits since it consumes the most power and leaks the most information against side-channel attacks. The proposed design is based on a delay-insensitive logic paradigm known as Null Convention Logic (NCL). The proposed NCL S-Box provides considerable benefits over existing designs since it consumes less power therefore suitable for energy-constrained mobile crypto-applications. It also emits less noise and has flatter power peaks therefore leaks less information against side-channel attacks such as differential power/noise analysis. Functional verification, analog simulation and power measurement of NCL S-Box have been done using Mentor Graphics EDA (Electronic Design Automation) tools to assure low-power side-channel attack-resistant operation of the proposed clock-free AES S-Box design.