IEEE Transactions on Computers
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
CRYPTO '96 Proceedings of the 16th Annual International Cryptology Conference on Advances in Cryptology
Resistance against Differential Power Analysis for Elliptic Curve Cryptosystems
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
A DPA Attack against the Modular Reduction within a CRT Implementation of RSA
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Power-Analysis Attack on an ASIC AES implementation
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
Low-Cost Solutions for Preventing Simple Side-Channel Analysis: Side-Channel Atomicity
IEEE Transactions on Computers
Parallel Cryptographic Arithmetic Using a Redundant Montgomery Representation
IEEE Transactions on Computers
Design and Analysis of Dual-Rail Circuits for Security Applications
IEEE Transactions on Computers
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Advances in Elliptic Curve Cryptography (London Mathematical Society Lecture Note Series)
Advances in Elliptic Curve Cryptography (London Mathematical Society Lecture Note Series)
A Scalable and High Performance Elliptic Curve Processor with Resistance to Timing Attacks
ITCC '05 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'05) - Volume I - Volume 01
Current mask generation: a transistor level security against DPA attacks
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Power Attacks on Secure Hardware Based on Early Propagation of Data
IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
Evaluation of Dynamic Voltage and Frequency Scaling as a Differential Power Analysis Countermeasure
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware
Proceedings of the conference on Design, automation and test in Europe
Investigations of power analysis attacks on smartcards
WOST'99 Proceedings of the USENIX Workshop on Smartcard Technology on USENIX Workshop on Smartcard Technology
RIJID: random code injection to mask power analysis based side channel attacks
Proceedings of the 44th annual Design Automation Conference
Power balanced gates insensitive to routing capacitance mismatch
Proceedings of the conference on Design, automation and test in Europe
Evaluation of the Masked Logic Style MDPL on a Prototype Chip
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems
Proceedings of the 20th symposium on Great lakes symposium on VLSI
A design methodology for secured ICs using dynamic current mode logic
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Masked dual-rail pre-charge logic: DPA-resistance without routing constraints
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Hi-index | 0.00 |
Side-channel attacks have become a prevalent research topic for electronic circuits in security-related applications, due to the strong correlation between data pattern and circuit external characteristics which can be easily measured. By monitoring the power/timing information of a synchronous circuit, an attacker can easily obtain the secret data stored on the device. Although dual-rail asynchronous circuits have more stable power traces, they are still vulnerable to power-based attacks because of the imbalanced loads between the two rails of each signal. Moreover, asynchronous circuits are among the most prone to timing attacks since their delays are strongly data dependent. Dual-spacer dual-rail delay-insensitive Logic (D^3L), presented in this paper, is able to mitigate both power- and timing-based side-channel attacks. In a D^3L circuit, power consumption is decoupled from data pattern by using a dual-spacer protocol which guarantees balanced switching activities between the two rails of each signal, while timing-data correlation is broken by inserting random delays. Three Advanced Encryption Standard cores have been designed using synchronous logic, traditional dual-rail asynchronous logic, and D^3L. Correlation Power Analysis and Timing Analysis attacks were applied and the results show that the D^3L design is able to render both attacks unsuccessful, while the other two circuits have vulnerabilities.