Evaluation of Dynamic Voltage and Frequency Scaling as a Differential Power Analysis Countermeasure

Authors:
Karthik Baddam;Mark Zwolinski
Affiliations:
University of Southampton, Southampton, UK;University of Southampton, Southampton, UK
Venue:
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Year:
2007

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Abstract

Differential Power Analysis (DPA) attack is a major concern for secure embedded devices [1] [3]. Currently proposed countermeasures [4] [10] to prevent DPA imposes significant area, power and performance overheads. In addition they either require special standard cell library and design flows or algorithmic modifications. Recently, Random Dynamic Voltage and Frequency Scaling (RDVFS) has been proposed [11] as a DPA countermeasure, which has less area, power and performance overheads and it does not require special cell library nor design flows nor algorithmic modifications. However, in a synchronous digital circuit, the operating frequency can be detected by monitoring glitches on the power line. In this paper, we show that using this information, it is possible to mount a DPA attack on circuits employing RDVFS countermeasure. We propose an alternative technique which only varies the supply voltage randomly. Experimental results on AES core with SPICE level simulations show that our proposed method significantly weakens the DPA attack by reducing the correlation of power to processed data.