CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks
IEEE Transactions on Dependable and Secure Computing
Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Evaluation of Dynamic Voltage and Frequency Scaling as a Differential Power Analysis Countermeasure
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks
IEEE Transactions on Computers
Protection Circuit against Differential Power Analysis Attacks for Smart Cards
IEEE Transactions on Computers
A table masking countermeasure for low-energy secure embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents an on-chip current flattening circuit designed in 0.18-@mm CMOS technology, which can be integrated with secure microsystems, such as smart cards, as a countermeasure against power analysis attacks. The robustness of the proposed countermeasure is evaluated by measuring the number of current traces required for a differential power analysis attack. We analyze the relationship between the required number of current traces and the dynamic current variations, and we show empirically that the required numbers of current traces is proportional to an inverse of the square of the rms value of the flattened current. Finally, we evaluate the effectiveness of the proposed design by using the experimental results of the fabricated chip. The analysis of the experimental results confirms the effectiveness of the current flattening circuit.