Reduction of substrate noise in sub clock frequency range
IEEE Transactions on Circuits and Systems Part I: Regular Papers
The effectiveness of a current flattening circuit as countermeasure against DPA attacks
Microelectronics Journal
FinFET-Based Power Management for Improved DPA Resistance with Low Overhead
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Synchronized attacks on multithreaded systems - application to java card 3.0 -
CARDIS'11 Proceedings of the 10th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
Utilizing random noise in cryptography: where is the tofu?
Proceedings of the International Conference on Computer-Aided Design
Towards trustworthy medical devices and body area networks
Proceedings of the 50th Annual Design Automation Conference
| Hi-index | 14.98 |
In this paper, we present a circuit that protects smart cards against differential power analysis attacks. The circuit is based on a current flattening technique, is designed using a standard 0.18-µm CMOS technology, and can be integrated on the same die or in the same package with the smart card microcontroller. We evaluate the current flattening performance and the effectiveness of the protection against differential power analysis attacks. Our analysis is based on transistor-level simulations in Cadence environment using experimental current traces collected from an 8-bit microcontroller for smart cards executing DES encryptions. The proposed circuit effectively protects against differential power analysis attacks with small chip area overhead and limited increased power consumption during the encryption cycles.