Substrate noise: analysis and optimization for IC design
Substrate noise: analysis and optimization for IC design
Proceedings of the 39th annual Design Automation Conference
Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits
Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits
Simultaneous switching noise in on-chip CMOS power distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and Implementation of a Server-Aided PKI Service (SaPKI)
AINA '05 Proceedings of the 19th International Conference on Advanced Information Networking and Applications - Volume 1
3D Chip Stack Technology Using Through-Chip Interconnects
IEEE Design & Test
Power Analysis Attacks and Countermeasures
IEEE Design & Test
Protection Circuit against Differential Power Analysis Attacks for Smart Cards
IEEE Transactions on Computers
Analysis and comparison on full adder block in submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Linear dependencies in extended LFSMs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance analysis of radix-4 adders
Integration, the VLSI Journal
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We propose a method of reducing the switching noise in the substrate of an integrated circuit. The main idea is to design the digital circuits to obtain a periodic supply current with the same period as the clock. This property locates the frequency components of the switching noise above the clock frequency. Differential return-to-zero signaling is used to reduce the data-dependency of the current. Circuits are implemented in symmetrical precharged DCVS logic with internally asynchronous D registers. A chip was fabricated in a standard 130-nm CMOS technology holding two versions of a pipelined 16-bit adder. First version employed the proposed method, and second version used conventional static CMOS logic circuits and TSPC registers. The respective device counts are 1190 and 684, and maximal operating frequencies 450 and 375 MHz. Frequency domain measurements were performed at the substrate node with on-chip generated sinusoidal and pseudo-random data at a clock frequency of 300 MHz. The sinusoidal case resulted in the largest frequency components, where an 8.5 dB/Hz decrease in maximal power is measured for the proposed circuitry at a cost of three times larger power consumption.