Circuit implementation of a 300-MHz 64-bit second-generation CMOS Alpha CPU
Digital Technical Journal - Special 10th anniversary issue
Effects of simultaneous switching noise on the tapered buffer design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High Performance Clock Distribution Networks
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
di/dt Noise in CMOS Integrated Circuits
Analog Integrated Circuits and Signal Processing - Special issue: analog design issues in digital VSLI circuits and systems
Analysis of the impact of bus implemented EDCs on on-chip SSN
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Empirical Validation of Yield Recovery Using Idle-Cycle Insertion
IEEE Design & Test
Modeling of on-chip bus switching current and its impact on noise in power supply grid
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clock-tree synthesis for low-EMI design
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Line width optimization for interdigitated power/ground networks
Proceedings of the 20th symposium on Great lakes symposium on VLSI
A three-step power-gating turn-on technique for controlling ground bounce noise
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Reduction of substrate noise in sub clock frequency range
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A novel design for evaluating simultaneous switching noise within an enhanced IBIS model
WSEAS Transactions on Circuits and Systems
EMC-aware design on a microcontroller for automotive applications
Proceedings of the Conference on Design, Automation and Test in Europe
Multi-layer interdigitated power distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing
Proceedings of the 48th Design Automation Conference
Power supply selective mapping for accurate timing analysis
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Spectral analysis of the on-chip waveforms to generate guidelines for EMC-aware design
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Clock distribution techniques for Low-EMI design
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Simultaneous switching noise reduction by resonant clock distribution networks
Integration, the VLSI Journal
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Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra large scale integration (VLSI/ULSI) circuits. An inductive model is used to characterize the power supply rails when a transient current is generated by simultaneously switching the on-chip registers and logic gates in a synchronous CMOS VLSI/ULSI circuit. An analytical expression characterizing the SSN voltage is presented here based on a lumped inductive-resistive-capacitive RLC model. The peak value of the SSN voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak value of the SSN voltage.