Circuit implementation of a 300-MHz 64-bit second-generation CMOS Alpha CPU

Electromigration reliability enhancement via bus activity distribution

DAC '96 Proceedings of the 33rd annual Design Automation Conference

High-performance, low-power design techniques for dynamic to static logic interface

ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design

Designing high bandwidth on-chip caches

Proceedings of the 24th annual international symposium on Computer architecture

Kin: a high performance asynchronous processor architecture

ICS '98 Proceedings of the 12th international conference on Supercomputing

Interconnect coupling noise in CMOS VLSI circuits

ISPD '99 Proceedings of the 1999 international symposium on Physical design

Selective cache ways: on-demand cache resource allocation

Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture

On the Yield of VLSI Processors with On-Chip CPU Cache

IEEE Transactions on Computers

Noise estimation due to signal activity for capacitively coupled CMOS logic gates

GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI

Wattch: a framework for architectural-level power analysis and optimizations

Proceedings of the 27th annual international symposium on Computer architecture

Value-based clock gating and operation packing: dynamic strategies for improving processor power and performance

ACM Transactions on Computer Systems (TOCS)

Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures

Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture

Cache decay: exploiting generational behavior to reduce cache leakage power

ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture

Let caches decay: reducing leakage energy via exploitation of cache generational behavior

ACM Transactions on Computer Systems (TOCS)

The Effect of Signal Activity on Propagation Delay of CMOS Logic Gates Driving Coupled On-Chip Interconnections

Analog Integrated Circuits and Signal Processing

Incorporating Voltage Fluctuations of the Power Distribution Network into the Transient Analysis of CMOS Logic Gates

Analog Integrated Circuits and Signal Processing

Runtime Reconfiguration Techniques for Efficient General-Purpose Computation

IEEE Design & Test

Superscalar Instruction Execution in the 21164 Alpha Microprocessor

IEEE Micro

Simultaneous switching noise in on-chip CMOS power distribution networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Clock Distribution Using Cooperative Ring Oscillators

ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)

Interconnect-Dominated VLSI Design

ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI

Incorporating Multi-Chip Module Packaging Constraints into System Design

EDTC '96 Proceedings of the 1996 European conference on Design and Test

RECAST: Boosting Tag Line Buffer Coverage in Low-Power High-Level Caches "for Free"

ICCD '05 Proceedings of the 2005 International Conference on Computer Design

Injection-locked clocking: a low-power clock distribution scheme for high-performance microprocessors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Custom circuit design as a driver of microprocessor performance

IBM Journal of Research and Development

Post-CTS delay insertion

VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems