The fanout problem: from theory to practice
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Circuit implementation of a 300-MHz 64-bit second-generation CMOS Alpha CPU
Digital Technical Journal - Special 10th anniversary issue
Delay bounded buffered tree construction for timing driven floorplanning
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
High speed CMOS design styles
Modeling microprocessor performance
Modeling microprocessor performance
IEEE Micro
Towards nanocomputer architecture
CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture
Optimum wire sizing of RLC interconnect with repeaters
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Optimum wire sizing of RLC interconnect with repeaters
Integration, the VLSI Journal
SCMP: a single-chip message-passing parallel computer
The Journal of Supercomputing - Special issue: Parallel and distributed processing and applications
| Hi-index | 0.00 |
This paper demonstrates the problems long, lossy wires pose for VLSI design as devices shrink to deep submicron dimensions. The degree to which both repeater insertion and reverse scaling of wire sizes are required to meet GHz clock frequency projections are estimated using a detailed wire distribution and a detailed processor model (RIPE). We also show how to achieve good floorplans with repeater insertion.