Evaluation of A+B=K Conditions Without Carry Propagation
IEEE Transactions on Computers
Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Conquering Noise in Deep-Submicron Digital ICs
IEEE Design & Test
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A 690ps Read-Access Latency Register File for a GHz Integer Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
Design Methodology for a 1.0 GHz Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
Circuit Design Techniques for a Gigahertz Integer Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
“Timing closure by design,” a high frequency microprocessor design methodology
Proceedings of the 37th Annual Design Automation Conference
Timed circuits: a new paradigm for high-speed design
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Automatic Abstraction for Verification of Timed Circuits and Systems
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Verification of Delayed-Reset Domino Circuits Using ATACS
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Interconnect-Dominated VLSI Design
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
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At the ISSCC98 conference the IBM Austin Research Laboratory presented an experimental 64-bit integer processor; guTS (GigaHertz unit Test Site). The goal of the guTS project was to demonstrate that circuit techniques, and circuit-centric design, could significantly increase the performance of microprocessors, thus providing headroom for future performance growth beyond contributions from microarchitecture and CMOS technology. The processor is a full-custom, nearly 100% dynamic design. Starting with a circuit family and a few components we went from high-level design to tapeout in half a year. About 16 designers participated, several part-time only. guTS implements 96 instructions from the integer subset of the PowerPC instruction set architecture, and covers in excess of 90% of instructions executed in typical code. Address translation, floating-point, and I/O related instructions are omitted. guTS is a single-issue core. All instructions, including loads and stores, execute in a single cycle. The focus of this article is on the circuit-centric design approach that enabled the GigaHertz result. We explain how design was done "vertically" rather than "horizontally", creating room for the "tall" designer that can operate across the boundaries of microarchitecture, logic-, circuit-, and physical design. We also explain why developments in CMOS technology increasingly favor this approach. We give an example of a circuit-centric vertically-integrated solution for both a problem in the control and a problem in the dataflow. We discuss how we created the design interfaces necessary to pursue aggressive circuits and we explain our choice of circuit families. We briefly discuss two chip integration issues that further challenge the way microprocessor designs are commonly partitioned.