“Timing closure by design,” a high frequency microprocessor design methodology
Proceedings of the 37th Annual Design Automation Conference
Delay-optimal wiring plan for the microprocessor of high performance computing machines
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
IEEE Micro
Verification of Delayed-Reset Domino Circuits Using ATACS
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Critical Path Identification and Delay Tests of Dynamic Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A metal and via maskset programmable VLSI design methodology using PLAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A design flow to optimize circuit delay by using standard cells and PLAs
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Crosstalk minimization in logic synthesis for PLAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power minimization for dynamic PLAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper describes the design methodology used to build an experimental 1.0 GigaHertz PowerPC integer microprocessor at IBM's Austin Research Laboratory. The high frequency requirements dictated the chip composition to be almost entirely custom macros using dynamic circuit techniques. The methodology presented will cover design and verification tools as well as circuit constraints and microarchitecture philosophy. The microarchitecture, circuits and tools were defined by the high frequency requirements of the processor as well as the aggressive design schedule and size of the design team.