Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA

Authors:
Hiroaki Yoshida;Hiroaki Yamaoka;Makoto Ikeda;Kunihiro Asada
Affiliations:
Department of Electronic Engineering, VLSI Design and Education Center(VDEC), University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan;Department of Electronic Engineering, VLSI Design and Education Center(VDEC), University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan;Department of Electronic Engineering, VLSI Design and Education Center(VDEC), University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan;Department of Electronic Engineering, VLSI Design and Education Center(VDEC), University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan
Venue:
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Year:
2002

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Abstract

In this paper, a new logic synthesis method for an AND-XOR-OR type sense-amplifying PLA is proposed. An AND-XOR-OR type sense-amplifying PLA can achieve low-power dissipation and high-speed operation by using latch sense-amplifiers and a charge sharing scheme. In addition, 2-input XOR function is conveniently implemented in place of the conventional AND/OR planes. Therefore it can realize some classes of logic functions in a smaller circuit area. Since the proposed method makes full use of the existing two-level logic minimization algorithms, it can handle large circuits such as 64-input Boolean function. The method has been implemented and the experimental results are presented. The experimental results show that some classes of Boolean functions can become much smaller and hence we can obtain significantly faster circuits than conventional PLAs with a small area penalty.