Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
A new method to express functional permissibilities for LUT based FPGAs and its applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
A novel VLSI layout fabric for deep sub-micron applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
DAC '84 Proceedings of the 21st Design Automation Conference
Design Methodology for a 1.0 GHz Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Performance-driven mapping for CPLD architectures
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Whirlpool PLAs: a regular logic structure and their synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Proceedings of the tenth international symposium on Hardware/software codesign
Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Crosstalk Minimization in Logic Synthesis for PLA
Proceedings of the conference on Design, automation and test in Europe - Volume 2
On designing via-configurable cell blocks for regular fabrics
Proceedings of the 41st annual Design Automation Conference
DEPOGIT: dense power-ground interconnect architecture for physical design integrity
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
PIM lite: a multithreaded processor-in-memory prototype
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A variation tolerant subthreshold design approach
Proceedings of the 42nd annual Design Automation Conference
A design flow to optimize circuit delay by using standard cells and PLAs
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Synthesis methodology for built-in at-speed testing
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Crosstalk minimization in logic synthesis for PLAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems
Journal of VLSI Signal Processing Systems
Pipelined network of PLA based circuit design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Designing via-configurable logic blocks for regular fabric
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a VLSI design methodology to address the cross-talk problem, which is becoming increasingly important in Deep Sub-Micron (DSM) IC design. In our approach, we implement the logic netlist in the form of a network of medium sized PLAs. We utilize two regular layout "fabrics" in our methodology, one for areas where PLA logic is implemented, and another for routing regions between such logic blocks. We show that a single PLA implemented in the first fabric style is not only cross-talk immune, but also about 2× smaller and faster than a traditional standard cell based implementation of the same logic. The second fabric, utilized in the routing region between individual PLAs, is also highly cross-talk immune. Additionally, in this fabric, power and ground signals are essentially "pre-routed" all over the die.Our synthesis flow involves decomposing the design into a network of PLAs, each of which has a bounded width and height. The number of inputs and outputs of each PLA are flexible as long as the resulting PLA width is bounded. We perform folding of PLAs to achieve better logic density. Routing is performed using 2, 3, 4, 5 and 6 routing layers. State-of-the-art commercial routing tools are utilized for the experiments involving the use of 3, 4, 5 and 6 routing layers.We have implemented the entire design flow using these ideas. Our scheme results in a reduction in the cross-talk between signal wires of between one and two orders of magnitude. As a result, for a 0.1μm process, the delay variation due to cross-talk dramatically drops from 2.47:1 to 1.02:1. Additionally, our methodology results in circuits that are extremely fast and dense, with a timing improvement of about 15% and an overall area penalty of about 3% compared to standard cells. The regular arrangement of metal conductors in our scheme results in low and highly predictable inductive and capacitive parasitics, resulting in highly predictable designs. The crosstalk immunity, high speed, low area overhead and high predictability of our methodology indicate that it is a strong candidate as the preferred design methodology in the DSM era.