Communications of the ACM
Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
STAC: statistical timing analysis with correlation
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Coping with The Variability of Combinational Logic Delays
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Gaining Predictability and Noise Immunity in Global Interconnects
ACSD '05 Proceedings of the Fifth International Conference on Application of Concurrency to System Design
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We discuss a new synthesis flow, which offers the ability to do easy delay testing almost free in terms of its impact on speed and area compared to corresponding implementations with standard cells. The methodology uses matched delays in pre-charged PLAs and bundled routing to produce a completion signal, which is guaranteed to lie on all critical paths. We give a nondelay testing method for ensuring matched delays are correct, i.e. that all completion signals arrive after their corresponding data signals. The design margins of the matched delays can be small since they are internal to the PLAs, which are regular structures and therefore more predictable.