DIVA: a reliable substrate for deep submicron microarchitecture design
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
ReVive: cost-effective architectural support for rollback recovery in shared-memory multiprocessors
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Pentium Pro Processor Design for Test and Debug
IEEE Design & Test
Design Challenges of Technology Scaling
IEEE Micro
Coverage-oriented verification of banias
Proceedings of the 40th annual Design Automation Conference
Microprocessor Entomology: A Taxonomy of Design Faults in COTS Microprocessors
DCCA '99 Proceedings of the conference on Dependable Computing for Critical Applications
Verification: what works and what doesn't
Proceedings of the 41st annual Design Automation Conference
Automatic generation of breakpoint hardware for silicon debug
Proceedings of the 41st annual Design Automation Conference
Millicode in an IBM zSeries processor
IBM Journal of Research and Development
A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special edition on the 15th international symposium on FPGAs
Online design bug detection: RTL analysis, flexible mechanisms, and evaluation
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Core monitors: monitoring performance in multicore processors
Proceedings of the 6th ACM conference on Computing frontiers
A memory system design framework: creating smart memories
Proceedings of the 36th annual international symposium on Computer architecture
Real-time lossless compression for silicon debug
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Specifying and dynamically verifying address translation-aware memory consistency
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
Using introspective software-based testing for post-silicon debug and repair
Proceedings of the 47th Design Automation Conference
Releasing efficient beta cores to market early
Proceedings of the 38th annual international symposium on Computer architecture
Accelerating microprocessor silicon validation by exposing ISA diversity
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Balancing Programmability and Silicon Efficiency of Heterogeneous Multicore Architectures
ACM Transactions on Embedded Computing Systems (TECS)
Runtime verification: a computer architecture perspective
RV'11 Proceedings of the Second international conference on Runtime verification
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Although processor design verification consumes ever-increasing resources, many design defects still slip into production silicon. In a few cases, such bugs have caused expensive chip recalls. To truly improve productivity, hardware bugs should be handled like system software ones, with vendors periodically releasing patches to fix hardware in the field. Based on an analysis of serious design defects in current AMD, Intel, IBM, and Motorola processors, this paper proposes and evaluates Phoenix -- novel field-programmable on-chip hardware that detects and recovers from design defects. Phoenix taps key logic signals and, based on downloaded defect signatures, combines the signals into conditions that flag defects. On defect detection, Phoenix flushes the pipeline and either retries or invokes a customized recovery handler. Phoenix induces negligible slowdown, while adding only 0.05% area and 0.48% wire overheads. Phoenix detects all the serious defects that are triggered by concurrent control signals. Moreover, it recovers from most of them, and simplifies recovery for the rest. Finally, we present an algorithm to automatically size Phoenix for new processors.