Core monitors: monitoring performance in multicore processors

  • Authors:

  • Paul E. West;Yuval Peress;Gary S. Tyson;Sally A. McKee

  • Affiliations:

  • Florida State University, Tallahassee, FL, USA;Floridat State University, Tallahassee, FL, USA;Florida State University, Tallahassee, FL, USA;Cornell University, Ithaca, NY, USA

  • Venue:
  • Proceedings of the 6th ACM conference on Computing frontiers
  • Year:
  • 2009

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Abstract

As we reach the limits of single-core computing, we are promised more and more cores in our systems. Modern architectures include many performance counters per core, but few or no inter-core counters. In fact, performance counters were not designed to be exploited by users, as they now are, but simply as aids for hardware debugging and testing during system creation. As such, they tend to be an "after thought" in the design, with no standardization across or within platforms. Nonetheless, given access to these counters, researchers are using them to great advantage [17]. Furthermore, evaluating counters for multicore systems has become a complex and resource consuming task. We propose a Performance Monitoring System consisting of a specialized CPU core designed to allow efficient collection and evaluation of performance data for both static and dynamic optimizations. Our system provides a transparent mechanism to change architectural features dynamically, inform the Operating System of process behaviors, and assist in profiling and debugging. For instance, a piece of hardware watching snoop packets can determine when a write-update cache coherence protocol would be helpful or detrimental to the currently running program. Our system is designed to allow the hardware to feed performance statistics back to software, allowing dynamic architectural adjustments at runtime.