DIVA: a reliable substrate for deep submicron microarchitecture design
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
ReVive: cost-effective architectural support for rollback recovery in shared-memory multiprocessors
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Opportunities and challenges for better than worst-case design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Complementary use of runtime validation and model checking
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Shielding against design flaws with field repairable control logic
Proceedings of the 43rd annual Design Automation Conference
Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Engineering trust with semantic guardians
Proceedings of the conference on Design, automation and test in Europe
Runtime Validation of Transactional Memory Systems
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures
IEEE Transactions on Dependable and Secure Computing
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A major challenge in hardware verification is managing the state explosion problem in pre-silicon verification. This is seen in the high cost and low coverage of simulation, and capacity limitations of formal verification. Runtime verification, through on-the-fly property checking of the current trace and a low-cost error recovery mechanism, provides us an alternative attack in dealing with this problem. There are several interesting examples of runtime verification that have been proposed in recent years in the computer architecture community. These have also been motivated by the resiliency needs of future technology generations in the face of dynamic errors due to device failures. I will first highlight the key ideas in hardware runtime verification through specific examples from the uni-processor and multi-processor contexts. Next, I will discuss the challenges in implementing some of these solutions. Finally I will discuss how the strengths of runtime verification and model checking can be used in a complementary fashion for hardware.