IEEE Design & Test
Designing UltraSparc for Testability
IEEE Design & Test
Alpha 21164 Testability Strategy
IEEE Design & Test
Test Features of the HP PA7100LC Processor
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Testabilty Features of the MC 68060 Microprocessor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Balancing Structured and Ad-hoc Design for Test: Testing of the PowerPC 603TM Microprocessor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
CIMMACS'07 Proceedings of the 6th WSEAS international conference on Computational intelligence, man-machine systems and cybernetics
Deterministic Replay Using Global Clock
ACM Transactions on Architecture and Code Optimization (TACO)
Formal-analysis-based trace computation for post-silicon debug
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 0.00 |
This article describes the Design for Test (DFT) and silicon debug features of the Pentium Pro processor, and its production test development methodology. The need to quickly ramp a complex, high-performance microprocessor into high-volume manufacturing with low defect rates led the design team to a custom low-area DFT approach, coupled with a manually-written test methodology which targeted several fault models. Results show that this approach was effective in balancing testability needs with other design constraints, while enabling excellent time to market and test quality.