Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays
IEEE Transactions on Computers
Detectability Conditions of Full Opens in the Interconnections
Journal of Electronic Testing: Theory and Applications
Mixed Signal DFT at GHz Frequencies
Journal of Electronic Testing: Theory and Applications
Pentium Pro Processor Design for Test and Debug
IEEE Design & Test
11.3 Mixed Signal DFT at GHz Frequencies
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
PENTIUM® PRO PROCESSOR DESIGN FOR TEST AND DEBUG
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Design-for-test techniques for opens in undetected branches in CMOS latches and flip-flops
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ZerehCache: armoring cache architectures in high defect density technologies
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
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The author describes device testing at Intel, a company that tests 50 million microprocessors a year. He notes some myths that have grown up around testing and addresses the challenges facing test engineers, test system designers, and researchers