Testability Conditions for Bilateral Arrays of Combinational Cells
IEEE Transactions on Computers
Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits
IEEE Transactions on Computers
Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model
IEEE Transactions on Computers
On the Testability of One-Dimensional ILAs for Multiple Sequential Faults
IEEE Transactions on Computers
A Functional Approach to Efficient Fault Detection in Iterative Logic Arrays
IEEE Transactions on Computers
Cell delay fault testing for iterative logic arrays
Journal of Electronic Testing: Theory and Applications
Testing CMOS combinational iterative logic arrays for realistic faults
Integration, the VLSI Journal
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
IEEE Design & Test
Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns
IEEE Transactions on Computers
Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Using ILA Testing for BIST in FPGAs
Proceedings of the IEEE International Test Conference on Test and Design Validity
Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits
Proceedings of the IEEE International Test Conference
Universal test complexity of field-programmable gate arrays
ATS '95 Proceedings of the 4th Asian Test Symposium
Segment delay faults: a new fault model
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Test of RAM-based FPGA: methodology and application to the interconnect
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers
Journal of Electronic Testing: Theory and Applications
Datapath BIST Insertion Using Pre-Characterized Area and Testability Data
Journal of Electronic Testing: Theory and Applications
The coupling model for function and delay faults
Journal of Electronic Testing: Theory and Applications
Efficient built-in self-test techniques for sequential fault testing of iterative logic arrays
AIC'06 Proceedings of the 6th WSEAS International Conference on Applied Informatics and Communications
Design-for-testability techniques for CORDIC design
Microelectronics Journal
Efficient built-in self-test techniques for sequential fault testing of iterative logic arrays
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
| Hi-index | 14.98 |
Iterative Logic Arrays (ILAs) are widely used in the datapath parts of digital circuits, like general purpose microprocessors, embedded processors, and digital signal processors. Testing strategies based on more comprehensive fault models than the traditional combinational fault models have become an imperative need in CMOS technology. In this paper, first, we introduce a comprehensive, cell-level, sequential fault model suitable for ILAs, termed Realistic Sequential Cell Fault Model (RS-CFM). RS-CFM drastically reduces test complexity compared to exhaustive two-pattern testing proposed so far in the literature for sequential ILA testing, without sacrificing test quality. In addition, it favors robustness of sequential test sets both at the cell and the array levels. Second, a new Automatic Test Pattern Generator (ILA-ATPG) based on RS-CFM for the case of one-dimensional ILAs is presented. ILA-ATPG can handle all classes of one-dimensional ILAs: unilateral or bilateral ILAs, with or without vertical inputs/outputs. Based on a graph model, ILA-ATPG explores the C-testability and linear-testability of the ILA under test and resolves the test invalidation problem constructing robust test sequences. The efficiency of ILA-ATPG is demonstrated through a comprehensive set of experimental results over all classes of one-dimensional ILAs, including all practical one-dimensional ILAs, as well as a number of more complex benchmarks.