Easily Testable Iterative Logic Arrays
IEEE Transactions on Computers
Testing CMOS combinational iterative logic arrays for realistic faults
Integration, the VLSI Journal
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays
IEEE Transactions on Computers
Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns
IEEE Transactions on Computers
An optimized BIST test pattern generator for delay testing
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
The Complexity of Fault Detection Problems for Combinational Logic Circuits
IEEE Transactions on Computers
Built-in sequential fault self-testing of array multipliers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In today's nanometer technology era, more sophicated defect mechanisms might exist in the manufactured integrated circuits which are not covered by traditional fault models. In order to ascertain the quality of shipped chips, more realistic fault models should be addressed. In this paper, we propose built-in self-test (BIST) techniques for iterative logic arrays (ILAs) based on realistic sequential cell fault model (RS-CFM). According to the proposed testability conditions and the adopted fault model, exhaustive SIC (single input change) pairs for a cell are applied to each cell in the ILA. The outputs can be propagated to the primary outputs and then observed. The SIC component generator and output response analyzer are also designed as the BIST circuitry. Due to the regularity of ILAs, the hardware overhead of the BIST circuitry is almost negligible. In order to illustrate our approach, a pipelined array multiplier is used as an example. The number of test pairs for completely testing of the array is only 72. Moreover, the BIST overhead to make it delay fault testable is about 1.67%.