Testing CMOS combinational iterative logic arrays for realistic faults

Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays

IEEE Transactions on Computers

8.1 Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Efficient built-in self-test techniques for sequential fault testing of iterative logic arrays

AIC'06 Proceedings of the 6th WSEAS International Conference on Applied Informatics and Communications

Efficient built-in self-test techniques for sequential fault testing of iterative logic arrays

IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems