Cell delay fault testing for iterative logic arrays
Journal of Electronic Testing: Theory and Applications
Testing CMOS combinational iterative logic arrays for realistic faults
Integration, the VLSI Journal
An Effective Built-In Self-Test Scheme for Parallel Multipliers
IEEE Transactions on Computers
Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns
IEEE Transactions on Computers
Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
ATPD: An Automatic Test Pattern Generator for Path Delay Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits
Proceedings of the IEEE International Test Conference
Robust Sequential Fault Testing of Iterative Logic Arrays
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
8.1 Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
On the detection of delay faults
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers
Journal of Electronic Testing: Theory and Applications
Efficient built-in self-test techniques for sequential fault testing of iterative logic arrays
AIC'06 Proceedings of the 6th WSEAS International Conference on Applied Informatics and Communications
Efficient built-in self-test techniques for sequential fault testing of iterative logic arrays
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
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Sequential fault testing approaches for array multipliers proposed in the past target only external testing and impose significant hardware overhead due to excessive DFT modifications. In this paper, we present, for first time, a BIST architecture which does not require any DFT modifications in the multiplier structure and provides a fault coverage larger than 99% for a comprehensive sequential fault model (RS-CFM) for any multiplier size. Both robust and non-robust testing are considered. The applicability of the BIST architecture is further justified considering the case of the transistor stuck-open fault model, where a fault coverage larger than 99% is also achieved in any case.