Easily Testable Iterative Logic Arrays
IEEE Transactions on Computers
Designing Self-Testable Cellular Arrays
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays
IEEE Transactions on Computers
Testing Schemes for FIR Filter Structures
IEEE Transactions on Computers
Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers
Journal of Electronic Testing: Theory and Applications
Robust Sequential Fault Testing of Iterative Logic Arrays
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
8.1 Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Efficient built-in self-test techniques for sequential fault testing of iterative logic arrays
AIC'06 Proceedings of the 6th WSEAS International Conference on Applied Informatics and Communications
Design-for-testability techniques for CORDIC design
Microelectronics Journal
Efficient built-in self-test techniques for sequential fault testing of iterative logic arrays
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
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Shows that a constant number of test vectors are sufficient for fully testing a k-dimensional ILA for sequential faults if the cell function is bijective. The authors then present an efficient algorithm to obtain such a test sequence. By extending the concept of C-testability and M-testability to sequential faults, the constant-length test sequence can be obtained. A pipelined array multiplier is shown to be C-testable with only 53 test vectors for exhaustively testing the sequential faults.