Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits

Fault simulation of interconnect opens in digital CMOS circuits

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays

IEEE Transactions on Computers

Improving bus test via IDDT and boundary scan

Proceedings of the 38th annual Design Automation Conference

Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits

Journal of Electronic Testing: Theory and Applications

Switch-level bridging fault simulation in the presence of feedbacks

ITC '98 Proceedings of the 1998 IEEE International Test Conference

An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

DELAY-FAULT TESTING AND DEFECTS IN DEEP SUB-MICRON ICS - DOES CRITICAL RESISTANCE REALLY MEAN ANYTHING?

ITC '00 Proceedings of the 2000 IEEE International Test Conference