Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Realistic fault modeling for VLSI testing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
E-PROOFS: a CMOS bridging fault simulator
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
A multiple-dominance switch-level model for simulation of short faults
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
The Logic Threshold Based Voting: A Model for Local Feedback Bridging Fault
EDCC-2 Proceedings of the Second European Dependable Computing Conference on Dependable Computing
Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits
Proceedings of the IEEE International Test Conference
Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Fast and Accurate CMOS Bridging Fault Simulation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
T4: New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
A fault model for switch-level simulation of gate-to-drain shorts
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Switch-level modeling of feedback faults using global oscillation control
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
IEEE Design & Test
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
Extraction and simulation of realistic CMOS faults using inductive fault analysis
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
An efficient CMOS bridging fault simulator: with SPICE accuracy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits
Journal of Electronic Testing: Theory and Applications
A Comparison of Bridging Fault Simulation Methods
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Modeling Feedback Bridging Faults with Non-Zero Resistance
Journal of Electronic Testing: Theory and Applications
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This paper investigates the degradation in detectabilityof bridging faults caused by situations of active feedbackand logically unresolvable intermediate values under differentfault modeling assumptions. A bridging fault simulatoris presented that is based on a combination of switch-levelmodeling and levelized logic simulation. Levelizedsimulation is efficient for fault propagation and feedbackanalysis, whereas the switch-level model is used for determiningwhether an intermediate value is logically resolvable.A method to extract the logic function of channelgraphs is presented in order to perform levelized processingof switch-level networks. The experimental results showthat active feedback may reduce fault coverage by as muchas 9% for stuck-at test sets and realistic bridging fault sets.