A multiple-dominance switch-level model for simulation of short faults

Authors:
Peter Dahlgren
Affiliations:
Department of Computer Engineering, Chalmers University of Technology, S-412 96 Gothenburg, Sweden
Venue:
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Year:
1995

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Abstract

Short faults in CMOS networks frequently give rise to intermediate node voltages. An efficient local algorithm is presented for event-driven switch-level simulation of CMOS networks in which intermediate signal values are common. The proposed model allows multiple dominant signals associated with the state of a node. The strength of several logical low and high signal contributions can thereby be taken into account when the logic state of a node is computed, which means that intermediate voltages can be handled more accurately. To demonstrate the usefulness of the multiple-dominance model in fault simulations, a new fault simulation algorithm is presented. Various common transistor-level fault types were simulated, and the results show that the number of discrepancies from electrical-level simulations is significantly reduced at a low computational cost.