A fault model for switch-level simulation of gate-to-drain shorts

Authors:
P. Dahlgren;P. Liden
Affiliations:
-;-
Venue:
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Year:
1996

Citing 0
Cited 2

Switch-level bridging fault simulation in the presence of feedbacks

ITC '98 Proceedings of the 1998 IEEE International Test Conference
Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting

Journal of Electronic Testing: Theory and Applications

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Abstract

An efficient algorithm for analyzing a subset of transistor-level bridging faults is proposed. The complex analogue behavior of gate-to-drain shorts is handled using a network primitive into which the fault injected transistor is mapped. The resistances of the surrounding subnetworks obtained from a linear switch-level model are used together with a simple iteration scheme to predict the voltage at the shortened nodes. Fault simulation experiments were conducted and the algorithm shows good agreement with electrical-level analysis.