E-PROOFS: a CMOS bridging fault simulator
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Logic Testing of Bridging Faults in CMOS Integrated Circuits
IEEE Transactions on Computers
Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Detection of Defects Using Fault Model Oriented Test Sequences
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
A novel algorithm to extract two-node bridges
Proceedings of the 37th Annual Design Automation Conference
Accurate Fault Modeling and Fault Simulation of Resistive Bridges
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Using Target Faults To Detect Non-Tartget Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
"Resistive Shorts" Within CMOS Gates
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
An Accurate Bridging Fault Test Pattern Generator
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Bridging Defects Resistance Measurements in a CMOS Process
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
BART: A Bridging Fault Test Generation for Sequential Circuits
Proceedings of the IEEE International Test Conference
Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Fast and Accurate CMOS Bridging Fault Simulation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Switch-level bridging fault simulation in the presence of feedbacks
ITC '98 Proceedings of the 1998 IEEE International Test Conference
CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Analyss of Dynamic Effects of Resistive Bridging Faults in CMOS and BiCMOS Digital ICs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
PROBE: A PPSFP Simulator for Resistive Bridging Faults
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Precise Test Generation for Resistive Bridging Faults of CMOS Combinational Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics
ISMVL '02 Proceedings of the 32nd International Symposium on Multiple-Valued Logic
The concept of resistance interval: a new parametric model for realistic resistive bridging fault
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A Comparison of Bridging Fault Simulation Methods
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Resistive Bridge Fault Modeling, Simulation and Test Generation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Bridging fault modeling and simulation for deep submicron CMOS ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Detectability of internal bridging faults in scan chains
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
SUPERB: Simulator utilizing parallel evaluation of resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
We study the behavior of feedback bridging faults with non-zero bridge resistance in both combinational and sequential circuits. We demonstrate that a test vector may detect the fault, not detect the fault or lead to oscillation, depending on bridge resistance. Moreover, the resistance intervals in which a particular behavior is observed are not necessarily contiguous. We demonstrate non-trivial behavior for situations in which a detection seems impossible, namely disabled loops going through a gate with controlling values on its side inputs.We outline the multiple strengths problem which arises due to the fact that a critical bridge resistance depends on the strengths of the signals driving the bridge, which in turn are functions of the number of the on-transistors, these again depending on the bridge resistance, making such a fault very hard to resolve. For sequential circuits, we describe additional difficulties caused by the need to account for implications on bridge behavior, which have originated in the previous time frames. We conclude that the complexity of resistive feedback bridging fault simulation accurate enough to resolve such situations will probably be prohibitively high and propose possible simplifying assumptions. We present simulation results for ISCAS benchmarks using these assumptions with and without taking oscillation into account.