Functional Tests for Scan Chain Latches
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
IC Defects-Based Testability Analysis
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Bridging Defects Resistance Measurements in a CMOS Process
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Bridging fault coverage improvement by power supply control
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
ATPG for scan chain latches and flip-flops
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
IDDQ Testability of Flip-flop Structures
IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
Iddq Test Pattern Generation for Scan Chain Latches and Flip-Flop
IDDQ '97 Proceedings of the 1997 IEEE International Workshop on IDDQ Testing (IDDQ '97)
The concept of resistance interval: a new parametric model for realistic resistive bridging fault
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Checking experiments to test latches
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Checking Experiments for Scan Chain Lathes and Flip-FLops
Checking Experiments for Scan Chain Lathes and Flip-FLops
A Comparison of Bridging Fault Simulation Methods
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Resistive Bridge Fault Modeling, Simulation and Test Generation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Automatic Test Pattern Generation for Resistive Bridging Faults
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
Modeling Feedback Bridging Faults with Non-Zero Resistance
Journal of Electronic Testing: Theory and Applications
Detecting FET Stuck-Open Faults in CMOS Latches And Flip-Flops
IEEE Design & Test
Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
IEEE Transactions on Computers
Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability
IEEE Transactions on Computers
On the Detectability of Scan Chain Internal Faults An Industrial Case Study
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Simulating Resistive-Bridging and Stuck-At Faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Scan chains contain a high percentage of the transistors in logic parts of VLSI designs. Nevertheless, faults inside scan cells are not directly targeted by scan based tests currently used, and they are assumed to be detected by what are called flush tests. Recently we investigated the detectability of stuck-at, stuck-on and stuck-open faults internal to scan chains using existing tests. We also proposed new flush tests and appropriate ordering of flush tests to achieve higher fault coverage. In this paper, we investigate detection of a set of scan cell internal bridging faults extracted from layout. We show that the detection of some zero-resistance non-feedback bridging faults requires two-pattern tests. Half-speed flush tests we proposed earlier to improve the coverage of stuck-at, stuck-on and stuck-open faults also detect additional bridging faults. We classify the undetectable faults based on the reasons for their undetectability. We observe that the driver strengths of the scan cell inputs can be optimized to improve the bridging fault coverage. Both zero-resistance and nonzero-resistance bridging fault models are considered in this work. A low power supply voltage based test method and IDDQ testing are examined for resistive bridging fault detection.