Checking experiments to test latches

  • Authors:
  • S. R. Makar;E. J. McCluskey

  • Affiliations:
  • -;-

  • Venue:
  • VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
  • Year:
  • 1995

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Abstract

Abstract: Necessary and sufficient conditions for exhaustive functional tests (checking experiments) of 2-state latches are derived. These conditions are used to derive minimum-length checking experiments. The checking experiment for the D-latch is simulated using an HSpice implementation of the transmission gate latch. All detectable shorted interconnects, open interconnects, short-to-power, short-to-ground, stuck-open, and stuck-on faults are detected. A pin fault test set and a multiplexer-based test set are also simulated. These tests miss some faults detected by the checking experiment.