Inside Spice: Overcoming the Obstacles of Circuit Simulation
Inside Spice: Overcoming the Obstacles of Circuit Simulation
CrossCheck: An Innovative Testability Solution
IEEE Design & Test
Functional Tests for Scan Chain Latches
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
IDDQ Testing in CMOS Digital ASIC's - Putting it All Together
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Detecting FET Stuck-Open Faults in CMOS Latches And Flip-Flops
IEEE Design & Test
Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
IEEE Transactions on Computers
Fault detecting experiments for sequential circuits
SWCT '64 Proceedings of the 1964 Proceedings of the Fifth Annual Symposium on Switching Circuit Theory and Logical Design
Detectability of internal bridging faults in scan chains
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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A new approach for testing the bistable elements (latches and flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking experiment to each bistable element in the circuit while checking their response. Such tests guarantee the detection of all detectable combinational defects inside the bistable elements. The algorithm is implemented by modifying an existing stuck-at combinational test pattern generator. The number of test patterns generated by the new program is comparable to the number of traditional stuck-at patterns. This shows that this approach is practical for large circuits.