Accelerated transition fault simulation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
On path selection in combinational logic circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
An Experimental Delay Test Generator for LSI Logic
IEEE Transactions on Computers
An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Delay Testing Considering Power Supply Noise Effects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Functions for Quality Transition Fault Tests
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Transition faults detection in bit parallel multipliers over GF(2m)
WSEAS Transactions on Circuits and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Design-for-testability techniques for CORDIC design
Microelectronics Journal
On the optimality of K longest path generation algorithm under memory constraints
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The class of faults known as gate delay faults are investigated in this paper. A taxonomy of the classes of gate delay fault detecting tests is provided. Methods to derive robust and non-robust tests to detect gate delay faults are proposed. A physically meaningful measure to assess the efficacy of test sequences is introduced, and used to report fault coverages.