Practical experiences from signal probability simulation of digital designs
DAC '77 Proceedings of the 14th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
The Effects of Races, Delays, and Delay Faults on Test Generation
IEEE Transactions on Computers
PERT as an aid to logic design
IBM Journal of Research and Development
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
A logic chip delay-test method based on system timing
IBM Journal of Research and Development
Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
Generation of tenacious tests for small gate delay faults in combinational circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
9.1 Efficient Path Selection for Delay Testing Based on Partial Path Evaluation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Multiple-Output Propagation Transition Fault Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Fault Diagnosis and Fault Model Aliasing
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Controllability of Static CMOS Circuits for Timing Characterization
Journal of Electronic Testing: Theory and Applications
Selection of a fault model for fault diagnosis based on unique responses
Proceedings of the Conference on Design, Automation and Test in Europe
Statistical delay fault coverage and defect level for delay faults
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
On the detection of delay faults
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Selection of a fault model for fault diagnosis based on unique responses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Diagnosis of transition fault clusters
Proceedings of the 48th Design Automation Conference
A high-precision on-chip path delay measurement architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 14.98 |
Delay testing is a test procedure to verify the timing performance of manufactured logic networks. When a level-sensitive scan design (LSSD) discipline is used, all networks are combinational. Appropriate test patterns are selected on the basis of certain theoretical criteria. These criteria are embodied in an experimental test generation program. The program has successfully produced sets of delay tests for large logic networks. The average coverage achieved by these tests faDs within 95.8 percent to 99.9 percent of optimal.