Parallel pattern fault simulation of path delay faults
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
The interdependence between delay-optimization of synthesized networks and testing
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Delay fault coverage and performance tradeoffs
DAC '93 Proceedings of the 30th international Design Automation Conference
Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Test Generation for Global Delay Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
An Experimental Delay Test Generator for LSI Logic
IEEE Transactions on Computers
Path delay fault testing of ICs with embedded intellectual property blocks
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 39th annual Design Automation Conference
Efficient Path Selection for Delay Testing Based on Path Clustering
Journal of Electronic Testing: Theory and Applications
Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
On theoretical and practical considerations of path selection for delay fault testing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Longest path selection for delay test under process variation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Experience in critical path selection for deep sub-micron delay test and timing validation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Critical Path Selection for Delay Testing Considering Coupling Noise
Journal of Electronic Testing: Theory and Applications
Path selection for transition path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits
Journal of Electronic Testing: Theory and Applications
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In this paper, we propose an efficient path selection method for path delay testing. The proposed method selects a very small set of paths for delay testing that covers all paths. Path selection is done by judging which of two paths has the larger real delay by taking into account the ambiguity of calculated delay, caused by imprecise delay modeling as well as process disturbance. In order to make precise judgement under this ambiguity, the delays of only unshared segments between the two paths are evaluated. This is because the shared segments are presumed to have the same real delays on both paths. Experimental results show the method can select about one percent of the paths selected by a conventional method without decreasing fault coverage.