Delay Testing for Non-Robust Untestable Circuits

Generation of high quality non-robust tests for path delay faults

DAC '94 Proceedings of the 31st annual Design Automation Conference

Synthesis of Delay-Verifiable Combinational Circuits

IEEE Transactions on Computers - Special issue on fault-tolerant computing

Fast identification of robust dependent path delay faults

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

On synthesis-for-testability of combinational logic circuits

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Quality considerations in delay fault testing

EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation

Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Generation of High Quality Tests for Robustly Untestable Path Delay Faults

IEEE Transactions on Computers

Testable path delay fault cover for sequential circuits

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

Test generation for primitive path delay faults in combinational circuits

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Fast identification of untestable delay faults using implications

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Delay Fault Coverage Enhancement Using Variable Observation Times

Journal of Electronic Testing: Theory and Applications

Deriving Logic Systems for Path Delay Test Generation

IEEE Transactions on Computers

On primitive fault test generation in non-scan sequential circuits

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

On Redundant Path Delay Faults in Synchronous Sequential Circuits

IEEE Transactions on Computers

On applying incremental satisfiability to delay fault testing

DATE '00 Proceedings of the conference on Design, automation and test in Europe

Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Efficient Path Selection for Delay Testing Based on Path Clustering

Journal of Electronic Testing: Theory and Applications

Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences

Journal of Electronic Testing: Theory and Applications

Identification of robust untestable path delay faults

ATS '95 Proceedings of the 4th Asian Test Symposium

Resynthesis of Combinational Circuts for Path Count Reduction and for Path Delay Fault Testability

EDTC '96 Proceedings of the 1996 European conference on Design and Test

A Fast Optimal Robust Path Delay Fault Testable Adder

EDTC '96 Proceedings of the 1996 European conference on Design and Test

Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences

ETW '00 Proceedings of the IEEE European Test Workshop

Diagnosis of parametric path delay faults

VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication

Parallel concurrent path-delay fault simulation using single-input change patterns

VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication

Identifying Redundant Path Delay Faults in Sequential Circuits

VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication

A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths

VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

Primitive Path Delay Fault Identification

VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

(Quasi-) Linear Path Delay Fault Tests for Adders

VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

9.1 Efficient Path Selection for Delay Testing Based on Partial Path Evaluation

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

9.3 Improving Path Delay Fault Testability by Path Removal

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

20.1 A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

A Flexible Path Selection Procedure for Path Delay Fault Testing

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Selection of Potentially Testable Path Delay Faults for Test Generation

ITC '00 Proceedings of the 2000 IEEE International Test Conference

On Invalidation Mechanisms for Non-Robust Delay Tests

ITC '00 Proceedings of the 2000 IEEE International Test Conference

ENHANCED DELAY DEFECT COVERAGE WITH PATH-SEGMENTS

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Exact Path Delay Grading with Fundamental BDD Operations

ITC '01 Proceedings of the 2001 IEEE International Test Conference

TESTING OF CRITICAL PATHS FOR DELAY FAULTS

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Efficient Identification of Non-Robustly Untestable Path Delay Faults

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Delay Testing with Clock Control: An Alternative to Enhanced Scan

ITC '97 Proceedings of the 1997 IEEE International Test Conference

ATPG for Path Delay Faults without Path Enumeration

ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design

Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults

IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)

Robust Testability of Primitive Faults using Test Points

ITC '99 Proceedings of the 1999 IEEE International Test Conference

A Statistical Fault Coverage Metric for Realistic Path Delay Faults

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium

A new classification of path-delay fault testability in terms of stuck-at faults

Journal of Computer Science and Technology

Yield-Driven, False-Path-Aware Clock Skew Scheduling

IEEE Design & Test

A yield improvement methodology using pre- and post-silicon statistical clock scheduling

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

On effective criterion of path selection for delay testing

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

An Improved Method for Identifying Linear Dependencies in Path Delay Faults

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

Diagnosis framework for locating failed segments of path delay faults

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

Testability driven statistical path selection

Proceedings of the 48th Design Automation Conference