Delay fault coverage and performance tradeoffs
DAC '93 Proceedings of the 30th international Design Automation Conference
Synthesis of Delay-Verifiable Combinational Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient Path Selection for Delay Testing Based on Path Clustering
Journal of Electronic Testing: Theory and Applications
Test Generation for Global Delay Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
Identification and Test Generation for Primitive Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Segment delay faults: a new fault model
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
On Invalidation Mechanisms for Non-Robust Delay Tests
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ENHANCED DELAY DEFECT COVERAGE WITH PATH-SEGMENTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
Testing the critical paths in a circuit is essential to coverdistributed delay and small delay defects in a manufacturedcircuit. However, in most circuits, only a small percentageof functionally irredundant critical paths (which can affectthe cycle time) are robustly testable. In this paper we proposethe covering of defects on untestable critical paths byrobustly testing the longest testable segments lying on thosepaths. This method is scalable to large circuits since thetask of segment delay fault test generation has complexitysimilar to path delay fault test generation. Experimental resultshave been given to demonstrate that significant additionalcoverage of defects on critical paths can be achievedusing this technique.