Synthesis of Delay-Verifiable Combinational Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Generation of High Quality Tests for Robustly Untestable Path Delay Faults
IEEE Transactions on Computers
Fast identification of untestable delay faults using implications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Fastpath: A Path-Delay Test Generator for Standard Scan Designs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Robustness Enhancement and Detection Threshold Reduction in ATPG for Gate Delay Faults
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A Generalized Test Generation Procedure for Path Delay Faults
FTCS '98 Proceedings of the The Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing
Test generation for resistive opens in CMOS
Proceedings of the 12th ACM Great Lakes symposium on VLSI
TESTING OF CRITICAL PATHS FOR DELAY FAULTS
ITC '01 Proceedings of the 2001 IEEE International Test Conference
On path-based learning and its applications in delay test and diagnosis
Proceedings of the 41st annual Design Automation Conference
Non-Enumerative Path Delay Fault Diagnosis
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Functions for Quality Transition Fault Tests
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A path-based methodology for post-silicon timing validation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
a fuzzy model for path delay fault detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
In most of the delay fault testing literature there isa widespread belief that a non-robust test for a pathdelay fault can be invalidated only through the existence of another path delay fault. In this paper wepresent an analysis of conditions that can invalidatea non-robust test, and present four different invalidation mechanisms. Three of these mechanisms, inaddition to the pulse dampening described in [1], donot require the existence of another path delay faultin a circuit. We also define pseudo-VNR tests, and weshow that this is the most common interpretation ofvalidatable-non-robust tests in literature. Uncovering the invalidation mechanisms for non-robust testsis quite important given the fact that a large numberof paths in a circuit usually do not have any robusttests.