Zero-suppressed BDDs for set manipulation in combinatorial problems
DAC '93 Proceedings of the 30th international Design Automation Conference
Synthesis of Delay-Verifiable Combinational Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Generation of High Quality Tests for Robustly Untestable Path Delay Faults
IEEE Transactions on Computers
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
On Invalidation Mechanisms for Non-Robust Delay Tests
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ATPG for Path Delay Faults without Path Enumeration
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Exact Grading of Multiple Path Delay Faults
Proceedings of the conference on Design, automation and test in Europe
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Path delay fault diagnosis in combinational circuits with implicit fault enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing-reasoning-based delay fault diagnosis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
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The first non-enumerative framework for diagnosing path delay faults using zero suppressed binary decision diagrams is introduced. We show that fault free path delay faults with a validated non-robust test may together with fault free robustly tested faults be used to eliminate faults from the set of suspected faults. All operations are implemented by an implicit diagnosis tool based on the zero suppressed binary decision diagram. The proposed method is space and time non-enumerative as opposed to existing methods which are space and time enumerative. Experimental results on the ISCASý85 benchmarks show that the proposed technique is on an average least three times more efficient to improve the diagnostic resolution than existing techniques.