The interdependence between delay-optimization of synthesized networks and testing
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A quantitative measure of robustness for delay fault testing
EURO-DAC '92 Proceedings of the conference on European design automation
Generation of high quality non-robust tests for path delay faults
DAC '94 Proceedings of the 31st annual Design Automation Conference
Synthesis of Delay-Verifiable Combinational Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Generation of High Quality Tests for Robustly Untestable Path Delay Faults
IEEE Transactions on Computers
A unified approach for timing verification and delay fault testing
A unified approach for timing verification and delay fault testing
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Line coverage of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Testing of critical paths for delay faults
Proceedings of the IEEE International Test Conference 2001
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
Fuzzy modeling in terms of surprise
Fuzzy Sets and Systems - Special issue: Interfaces between fuzzy set theory and interval analysis
Segment delay faults: a new fault model
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
On Invalidation Mechanisms for Non-Robust Delay Tests
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Circuit and Platform Design Challenges in Technologies beyond 90nm
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Test enrichment for path delay faults using multiple sets of target faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Energy models for delay testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A fuzzy model is proposed to analyze the effectiveness of test pairs targeting path delay faults. This model is accurate enough to rank nonrobust tests by accounting for conditions not considered in existing models. It remains fully consistent with the traditional test robustness analysis. Finally, it also provides a coverage metric to be used to rank whole test sets. The proposed model has been implemented in a logic level path delay fault simulator. Its accuracy has been validated, for a set of combinational benchmarks, by means of a Monte Carlo logic-level event-driven path delay fault simulator.