Test generation for resistive opens in CMOS
Proceedings of the 12th ACM Great Lakes symposium on VLSI
What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit?
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A Statistical Fault Coverage Metric for Realistic Path Delay Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
TranGen: a SAT-based ATPG for path-oriented transition faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Propagation delay fault: a new fault model to test delay faults
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Timing-based delay test for screening small delay defects
Proceedings of the 43rd annual Design Automation Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Proceedings of the Conference on Design, Automation and Test in Europe
a fuzzy model for path delay fault detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 0.00 |
We propose a new coverage metric for delay fault tests. The coverage is measured for each line with a rising and a falling transition, but the test criterion differs from that of the slow-to-rise and slow-to-fall transition faults. A line is tested by a line delay test, which is a robust path delay test for the longest sensitizable path producing a given transition on the target line. Thus, the test criterion resembles path delay test and not the gate or transition delay test. Yet, the maximum number of tests (or faults) is limited to twice the number of lines. In a two-pass test-generation procedure, we first attempt delay tests for a minimal set of longest paths for all lines. Fault simulation is used to determine the coverage metric. For uncovered lines, in the second pass, several paths of decreasing lengths are targeted. We give results for several benchmark circuits.