Line coverage of path delay faults

  • Authors:
  • Ananta K. Majhi;Vishwani D. Agrawal;James Jacob;Lalit M. Patnaik

  • Affiliations:
  • Philips Research Labs, Eindhoven, The Netherlands;Bell Labs, Lucent Technologies, Murray Hill, NJ;Intel Corp., Hillsboro, OR;Indian Institute of Science, Bangalore, India

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
  • Year:
  • 2000

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Abstract

We propose a new coverage metric for delay fault tests. The coverage is measured for each line with a rising and a falling transition, but the test criterion differs from that of the slow-to-rise and slow-to-fall transition faults. A line is tested by a line delay test, which is a robust path delay test for the longest sensitizable path producing a given transition on the target line. Thus, the test criterion resembles path delay test and not the gate or transition delay test. Yet, the maximum number of tests (or faults) is limited to twice the number of lines. In a two-pass test-generation procedure, we first attempt delay tests for a minimal set of longest paths for all lines. Fault simulation is used to determine the coverage metric. For uncovered lines, in the second pass, several paths of decreasing lengths are targeted. We give results for several benchmark circuits.