Line coverage of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Very-Low-Voltage Testing for Weak CMOS Logic ICs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
High-Frequency, At-Speed Scan Testing
IEEE Design & Test
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs
IEEE Design & Test
Reducing Pattern Delay Variations for Screening Frequency Dependent Defects
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
On Hazard-free Patterns for Fine-delay Fault Testing
ITC '04 Proceedings of the International Test Conference on International Test Conference
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
ALAPTF: A NEW TRANSITION FAULTMODEL AND THE ATPG ALGORITHM
ITC '04 Proceedings of the International Test Conference on International Test Conference
A novel faster-than-at-speed transition-delay test method considering IR-drop effects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An on-chip clock generation scheme for faster-than-at-speed delay testing
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects
Proceedings of the Conference on Design, Automation and Test in Europe
CδIDDQ: improving current-based testing and diagnosis through modified test pattern generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GPU-based n-detect transition fault ATPG
Proceedings of the 50th Annual Design Automation Conference
AC-plus scan methodology for small delay testing and characterization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. These small delay defects might be activated on longer paths during functional operation and cause a timing failure. This paper presents an improved pattern generation technique for transition fault model, which provides a higher coverage of small delay defect that lie along the long paths, using a commercial no-timing ATPG tool. The proposed technique pre-processes the scan flip-flops based on their least slack path and the detectable delay defect size. A new delay defect size metric based on the affected path length and required increase in test frequency is developed. We then perform pattern generation and apply a novel pattern selection technique to screen test patterns affecting longer paths. Using this technique will provide the opportunity of using existing timing unaware ATPG tools as slack based ATPG. The resulting pattern set improves the defect screening capability of small delay defects.