AC-plus scan methodology for small delay testing and characterization

Authors:
Tsung-Yeh Li;Shi-Yu Huang;Hsuan-Jung Hsu;Chao-Wen Tzeng;Chih-Tsun Huang;Jing-Jia Liou;Hsi-Pin Ma;Po-Chiun Huang;Jenn-Chyou Bor;Ching-Cheng Tien;Chih-Hu Wang;Cheng-Wen Wu
Affiliations:
Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan;Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan;Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan;Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan;Computer Science Department, National Tsing Hua University, Hsinchu, Taiwan;Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan;Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan;Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan;Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan;Electrical Engineering Department, Chung Hua University, Hsinchu, Taiwan;Electrical Engineering Department, Chung Hua University, Hsinchu, Taiwan;Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2013

Citing 24
Cited 0

Delay Fault Coverage Enhancement Using Variable Observation Times

Journal of Electronic Testing: Theory and Applications
Enhancing test efficiency for delay fault testing using multiple-clocked schemes

Proceedings of the 39th annual Design Automation Conference
Delay Testing with Double Observations

ATS '98 Proceedings of the 7th Asian Test Symposium
Test Method Evaluation Experiments & Data

ITC '00 Proceedings of the 2000 IEEE International Test Conference
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation

ITC '99 Proceedings of the 1999 IEEE International Test Conference
High-Frequency, At-Speed Scan Testing

IEEE Design & Test
Delay Defect Characteristics and Testing Strategies

IEEE Design & Test
Delay Defect Screening using Process Monitor Structures

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs

IEEE Design & Test
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Towards an Understanding of No Trouble Found Devices

VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
On Hazard-free Patterns for Fine-delay Fault Testing

ITC '04 Proceedings of the International Test Conference on International Test Conference
Enhanced Timing-Based Transition Delay Testing for Small Delay Defects

VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
The good, the bad, and the ugly of silicon debug

Proceedings of the 43rd annual Design Automation Conference
Timing-based delay test for screening small delay defects

Proceedings of the 43rd annual Design Automation Conference
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects

ATS '06 Proceedings of the 15th Asian Test Symposium
Transition Fault Simulation

IEEE Design & Test
An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing

ATS '07 Proceedings of the 16th Asian Test Symposium
Built-In Speed Grading with a Process-Tolerant ADPLL

ATS '07 Proceedings of the 16th Asian Test Symposium
Small-delay defect detection in the presence of process variations

Microelectronics Journal
Test-Pattern Grading and Pattern Selection for Small-Delay Defects

VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Optimal margin computation for at-speed test

Proceedings of the conference on Design, automation and test in Europe
A New Post-Silicon Debug Approach Based on Suspect Window

VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Output Hazard-Free Transition Delay Fault Test Generation

VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium

Quantified Score

Hi-index	0.00

Visualization

Abstract

Small delay defects escaping traditional delay testing could cause a device to malfunction in the field and thus detecting these defects is often necessary. To address this issue, we propose three test modes in a new methodology called AC-plus scan, in which versatile test clocks can be generated on the chip by embedding an all-digital phase-locked loop (ADPLL) into the circuit under test (CUT). AC-plus scan can be executed on an in-house wireless test platform called HOY system. The first test mode of our AC-plus scan provides a more efficient way to measure the longest path delay associated with each test pattern. Experimental result shows that our method could greatly reduce the test time by 81.8%. The second test mode is designed for volume production test. It could effectively detect small delay defects and provide fast characterization on those defective chips for further processing. This mode could be used to help predict which chips are more likely to fall victim to operational failure in the field. The third test mode is to extract the waveform of each flip-flop's output in a real chip. This is made possible by taking advantage of the almost unlimited test memory our HOY test platform provides, so that we could easily store a great volume of data and reconstruct the waveform for post-silicon debugging. We have successfully fabricated a Viterbi decoder chip with such an AC-plus scan methodology inside to demonstrate its capability.