Scan-Based Transition Fault Testing " Implementation and Low Cost Test Challenges
ITC '02 Proceedings of the 2002 IEEE International Test Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Process and environmental variation impacts on ASIC timing
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical static timing analysis using Markov chain Monte Carlo
Proceedings of the Conference on Design, Automation and Test in Europe
A physical-location-aware fault redistribution for maximum IR-drop reduction
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A physical-location-aware X-bit redistribution for maximum IR-drop reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
AC-plus scan methodology for small delay testing and characterization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In the face of increased process variations, at-speed manufacturing test is necessary to detect subtle delay defects. This procedure necessarily tests chips at a slightly higher speed than the target frequency required in the field. The additional performance required on the tester is called test margin. There are many good reasons for margin including voltage and temperature requirements, incomplete test coverage, aging effects, coupling effects and accounting for modeling inaccuracies. By taking advantage of statistical timing, this paper proposes an optimal method of test margin determination to maximize yield while staying within a prescribed Shipped Product Quality Loss (SPQL) limit. If process information is available from wafer testing of scribe line structures or on-chip process monitoring circuitry, this information can be leveraged to determine a per-chip test margin which can further improve yield.